Semiconductor device and method of manufacturing such a device

ABSTRACT

The invention relates to a so-termed punchthrough diode ( 10 ) with a stack of, for example, n++, n−, p+, n++ regions ( 1,2,3,4 ). In the known diode, these semiconductor regions ( 1,2,3,4 ) are positioned in said order on a substrate ( 11 ). The diode is provided with connection conductors ( 5,6 ). Such a diode does not have a steep I-V characteristic and is therefore less suitable as a TVSD (=Transient Voltage Suppression Device). In particular at voltages below 5 volts, a punchthrough diode could form an attractive alternative as TVSD. In a punchthrough diode ( 10 ) according to the invention, a part of the first semiconductor region ( 1 ) bordering on the second semiconductor region ( 2 ) comprises a number of sub-regions ( 1 A) which are separated from each other by a further semiconductor region ( 7 ) of the second, for example p+, conductivity type which is electrically connected to the first connection conductor ( 5 ). Such a diode has a very steep I-V characteristic, is very suitable as a TVSD and functions very well at an operating voltage below 5 volts. Preferably, the further region ( 7 ) comprises a part ( 7 A) which is wider than the other parts thereof. The regions ( 1,2,3,4 ) may be present in two different orders within a stack positioned on the substrate ( 11 ), each of said orders having certain advantages.

The invention relates to a semiconductor device with a substrate and asemiconductor body comprising, in succession, a first semiconductorregion of a first conductivity type and having a first dopingconcentration, a second semiconductor region having a second dopingconcentration which is lower than the first doping concentration, athird semiconductor region of a second conductivity type, opposite tothe first conductivity type, and having a third doping concentrationranging between the first and the second doping concentration, and afourth semiconductor region of the first conductivity type and having afourth doping concentration which is higher than the third dopingconcentration, wherein the first and the fourth semiconductor region areeach provided with an electric connection conductor one of which issituated on the side of the substrate and the other of which is situatedon the surface of the semiconductor body and across which an electricvoltage is applied during operation of the device, wherein the thicknessand the doping concentration of the second and the third semiconductorregion are chosen such that these regions are completely depleted duringoperation. Such a device, also referred to as punchthrough diode, is anattractive alternative to Zener diodes, in particular at an operatingvoltage below approximately 5 volts, as a suppressor of peak voltagesowing to its steep punchthrough characteristic and low capacitance.

The invention also relates to a method of manufacturing such a device.

Such a device is known from United States patent specification U.S. Pat.No. 4,405,932, published on 20 Sep. 1983. In said document a descriptionis given of a diode with a n+ substrate that comprises the firstsemiconductor region, on which a stack of the second, third and fourthsemiconductor region is situated, being an n− region, a p region and ann+ region, respectively. The substrate and the n+ region are providedwith connection conductors. The n− region comprises an epitaxial layerwherein the p− region is formed as a recessed region; in said p-regionin turn the n+ region is formed as a recessed region.

Experiments have shown that a drawback of the known device resides inthat the I-V (=Current-Voltage) characteristic of the diode does notexhibit the desired variation, i.e. the transition is not straight andsteep, in particular if the diode is designed such that the so-termedpunchthrough voltage is above 2 volts. Also the behavior of the diode isnot stable.

Therefore it is an object of the present invention to provide a deviceof the type mentioned in the opening paragraph in which said drawback is(at least partly) obviated and which has a very straight and steep I-Vcharacteristic, and wherein the punchthrough voltage is above 2 volts,and which is very stable.

To achieve this, in accordance with the invention, a device of the typementioned in the opening paragraph is characterized in that a part ofthe first semiconductor region bordering on the second semiconductorregion comprises a number of sub-regions which are separated from eachother by a further semiconductor region of the second conductivity typewhich is electrically connected to the first connection conductor. Ithas been found that such a device has a very steep I-V characteristicalso at a design voltage above 2 volts. The invention is based, interalia, on the following recognition. A punchthrough diode can be regardedas a bipolar transistor with an open base, i.e. without a baseconnection. If a forward voltage is applied to the device, the junctionbetween the (lightly doped) p− region and the n++ region, or in theevent of a lightly doped n− region instead of a lightly doped p− region,the junction between the p+ and the n− region, is slightlyforward-poled. This means that the n++ region then serves as the emitterof the transistor, the p+ region as the base and the p− region as a partof the base, and the n++ substrate forms the collector. If thecollector-emitter breakdown voltage of the transistor (=BVCEO) is lowerthan the punchthrough voltage at any current strength, the diode willexhibit a negative resistance behavior. This may cause instability, suchas undesirable oscillation. A relation between the BVCEO and thejunction breakdown voltage (=BVCBO) is: BVCEO=BVCBO/β^(1/n), where β isthe current gain that is equal to the quotient of the base current (ib)and the collector current (ic) and n has a value in the range between 3and 4. The base current is determined by the recombination of holes andelectrons in the lightly doped region, i.e. the p− region or the n−region. In the known diode, the current gain may be very high, which isattributable in particular to the fact that the base region issubstantially or partly depleted, and in addition to the fact that therecombination in said regions is very low due to the long recombinationlifetime of charge carriers in (bulk) silicon. In addition, the lateraldiffusion-capability of holes is limited because the base region isdepleted during operation. As a result, BVCEO is low. In a device inaccordance with the invention, on the one hand, the furthersemiconductor region, which is of the p conductivity type in the examplediscussed, provides an escape route for the holes generated by impactionization. As this region is, as it were, distributed over the firstsemiconductor region, this escape route is present everywhere and theholes need not bridge a distance, at least in the lateral direction, toreach the escape route and can readily flow from the base to theemitter. As the holes can be readily drained, the base current isincreased and hence the gain reduced. The occurrence ofcollector-emitter breakdown is thus precluded and hence also theoccurrence of instability (oscillation) caused by negative resistancebehavior. On the other hand, the first, n-type, semiconductor regionthat is divided into parts still provides excellent contact for the mainconstituent of the electric current through the device, i.e. theelectron current. As a result, the I-V characteristic is very steep,which is highly desirable.

The, for example p+, parts of the further semiconductor region mayextend up to the (p-type) base region. However, this is not necessary.An advantage of a separation between these parts and the base region bymeans of the lightly doped n− layer, which is sufficiently highly dopednot to be depleted already at 0 volt, resides in that the capacitance ofthe punchthrough diode in accordance with the invention can beminimized.

In a first particularly advantageous embodiment, the substrate comprisesa semiconductor substrate of the first conductivity type that borders onthe first semiconductor region, and the semiconductor body comprisesanother semiconductor region of the first conductivity type having ahigher doping concentration than the substrate, which othersemiconductor region is connected to the substrate and, by means of thefirst electric conductor, to the further semiconductor region. In thismodification the, p-type, base region is situated close to the surfaceof the semiconductor body. This has the advantage that this region canbe readily formed by means of a very well defined ion implantation. As aresult, the punchthrough voltage, that depends directly on the dopingconcentration of the base region, can be readily and accuratelydetermined. An important additional advantage of this modificationresides in that different voltage regulators/ESD (=Electro StaticDischarge) protection devices are integrated in the same semiconductorbody. The further semiconductor region, which is buried in thismodification, can be brought to the voltage level of the collectorregion by means of a separate connection region. Preferably, however,like in this modification, the further semiconductor region isshort-circuited with the substrate via a conductor (metal).

In a different modification the substrate comprises a semiconductorsubstrate of the first conductivity type and the fourth semiconductorregion, and the further semiconductor region borders directly on thefirst conductor. This modification, wherein the emitter region of thepunchthrough diode borders on the surface of the semiconductor body, hasthe advantage that the manufacture of the device is comparatively simplebecause the semiconductor layer structure can be formed in a single(epitaxial) growth process. In addition, the manufacture is verycompatible with that of present-day bipolar transistors, such as thosemanufactured in BiCMOS (Bipolar Complementary Metal Oxide Semiconductor)technology. An additional advantage of this modification resides in thatthe n+ region separating the base region from a connection conductor canreadily be made so as to be very thin. The hole current can thus readilyrecombine at the interface between the semiconductor material, such assilicon, and the metal of the conduction conductor. As a result, thecurrent gain is slightly further reduced.

In both said modifications, preferably, a part of the furthersemiconductor region that borders on a sub-region of the firstsemiconductor region has a larger width than the other parts of thefurther semiconductor region. By virtue thereof, the so-termed clampingcharacteristic of a device in accordance with the invention can bereadily controlled in the reverse direction. In such a case, theelectron current flows substantially uniformly through the base regionsince this has a uniform potential. As a result, a small voltage dropwill occur under the wide part of the p+ region because the electroncurrent must pass through the comparatively wide, lightly doped n−region. At a certain current intensity, this voltage drop is such thatit causes the p+/n junction to become forward-poled, and the associatedhole current will now drive the intrinsic npn transistor. As a result, asudden decrease of the clamping voltage occurs. The wide(r) part of thefurther semiconductor region may be positioned everywhere/anywhere, butis preferably located at the edge of the device. This has the advantagethat the influence of any alignment errors in the manufacturing process,which normally manifest themselves at the edge, is comparatively small.A suitable width of the wider part ranges between 5 and 20 μm, and theother parts of the further semiconductor region preferably have a widthin the range of 1 to 5 μm. The latter width is preferably also used forthe width of the sub-regions of the first semiconductor region. Asalready indicated hereabove, the first conductivity type preferably isthe n-conductivity type. This has the advantage that maximum advantagecan be made of the greater mobility of electrons as compared to holes.

A method of manufacturing a semiconductor device, wherein asemiconductor body with a substrate is formed, wherein there is formedin the semiconductor body, in this order, a first semiconductor regionof a first conductivity type and having a first doping concentration, asecond semiconductor region having a second doping concentration that islower than the first doping concentration, a third semiconductor regionof a second conductivity type, which is opposite to the firstconductivity type, and having a third doping concentration rangingbetween the first and the second doping concentration, and a fourthsemiconductor region of the first conductivity type and having a fourthdoping concentration that is higher than the third doping concentration,wherein the first and the fourth semiconductor region are provided withan electric connection conductor across which an electric voltage isapplied during operation of the device, and wherein the thickness andthe doping concentration of the second semiconductor region are chosensuch that, during operation, the second semiconductor region iscompletely depleted, is characterized in accordance with the inventionin that a part of the first semiconductor region that borders on thesecond semiconductor region is divided into a number of sub-regionswhich are separated from each other by a further semiconductor region ofthe second conductivity type which is connected to the first connectionconductor. In this manner a device in accordance with the invention isobtained.

In a favorable modification thereof, a semiconductor substrate of thefirst conductivity type is chosen as the substrate, and the firstsemiconductor region is formed thereby. In the semiconductor bodyanother semiconductor region of the first conductivity type is formedhaving a higher doping concentration than the substrate, which othersemiconductor region is connected to the substrate and, by means of thefirst electric conductor, to the further semiconductor region. A devicein accordance with the invention having the above-discussed advantagesis thus obtained.

In another modification, on the substrate a lightly doped epitaxialsemiconductor layer is applied, which is provided with the secondconductivity type by means of an ion implantation that reaches at leastas far as the substrate, and wherein the sub-regions of the firstsemiconductor region and the other semiconductor region are formed bymeans of a further ion implantation that reaches at least as far as thesubstrate, after which the second, third and fourth semiconductor regionare formed by means of epitaxy, a part of the second, third and fourthsemiconductor region situated above the other semiconductor region areremoved, and the electric conductors are provided.

This method is comparatively simple and compatible with the customaryprocesses in the silicon technology.

In a further modification, a semiconductor substrate of the firstconductivity type is chosen as the substrate and, as a result, thefourth semiconductor region is formed and the further semiconductorregion which borders directly on the first conductor is formed.

Preferably, the third, second and first semiconductor region aresuccessively provided on the substrate by means of epitaxy, whereafterthe further semiconductor region is formed in the first semiconductorregion by means of ion implantation, after which the electric conductorsare provided. This method comprises comparatively few steps and isconsequently attractive.

In all modifications, preferably one of the parts of the furthersemiconductor region which border on a sub-region of the firstsemiconductor region is provided with a larger width than the otherparts. By virtue thereof, the properties of a device in accordance withthe invention can be controlled in the reverse direction.

These and other aspects of the invention are apparent from and will beelucidated with reference to the embodiment(s) described hereinafter.

In the drawings:

FIG. 1 is a diagrammatic, cross-sectional view at right angles to thethickness direction, of a first example of a semiconductor device inaccordance with the invention,

FIG. 2 is a diagrammatic, cross-sectional view taken on the line II-IIof the device shown in FIG. 1,

FIG. 3 is a diagrammatic, cross-sectional view taken on the line III-IIIof the variation of the doping concentration in the device of FIG. 1,

FIGS. 4 through 10 are diagrammatic, cross-sectional views at rightangles to the thickness direction, of the device of FIG. 1 in successivestages of the manufacture by means of a method in accordance with theinvention,

FIG. 11 is a diagrammatic, cross-sectional view at right angles to thethickness direction, of a second example of a semiconductor device inaccordance with the invention, and

FIG. 12 shows the current density (J) as a function of the voltage (B)of the device of FIG. 11 for different values of the width of the widestpart of the further semiconductor region.

The Figures are not drawn to scale and particularly the dimensions inthe thickness direction are exaggerated for clarity. Correspondingregions are indicated by means of the same reference numerals wheneverpossible, and regions having the same conductivity type are generallyindicated by means of the same hatching pattern.

FIG. 1 is a diagrammatic, cross-sectional view at right angles to thethickness direction, of a semiconductor device in accordance with theinvention. Said device, a so-termed punchthrough diode, comprises asemiconductor body 12 with an n+ silicon semiconductor substrate 11 anda series of semiconductor regions 1, 2, 3, 4, being, respectively, ann++ region 1, an n− region 2, a p+ region 3 and an n++ region 4. Thediode is provided with two connection conductors 5, 6. During operationof the diode an electric voltage is applied across it, and the thicknessand the doping concentration of the second and the third semiconductorregion 2, 3 are chosen such that they are depleted during operation.

In accordance with the invention, the first semiconductor region 1comprises a number of sub-regions 1A which are separated from each otherand surrounded by a p-type further semiconductor region 7. Said furthersemiconductor region 7 is connected to the first connection conductor 5which is also connected, via another n++ semiconductor region 8 and viathe substrate 11, to the first semiconductor region 1. FIG. 2 shows thesub-regions 1A of the first semiconductor region 1, which are surroundedby the further semiconductor region 7. In FIG. 2 seven sub-regions 1Aare shown, but only three thereof are shown in FIG. 1 for the sake ofsimplicity. It has been found that such a device has a particularlysteep I-V characteristic, also if the design voltage is above 2 volts,as a result of which the device may be used, and is very attractiveeven, as an alternative to Zener diodes for suppressing voltage peaks.The invention is based on the following recognition.

The punchthrough diode 10 may be regarded as a bipolar transistor withan open base 3, i.e. without a base connection. If a forward voltage isapplied to the device, the junction between the p+ region 9 and the n−region 2 is slightly forward-poled. This means that the n++ region 4then acts as an emitter of the transistor, the p+ region as the base andthe n− region 2 and the n++ region 1 form the collector. If thecollector-emitter breakdown voltage of the transistor (=BVCEO) is lowerthan the punchthrough voltage at any current intensity, the diode 10will exhibit a negative resistance behavior. This may cause instabilitysuch as an undesirable oscillation. A relation between the BVCEO and thejunction breakdown voltage (=BVCBO) is: BVCEO=BVCBO/β^(1/n), wherein βis the current gain that is equal to the quotient of the base current(ib) and the collector current (ic) and n has a value in the rangebetween 3 and 4. The base current is determined by the recombination ofholes and electrons in the lightly doped region 2, i.e. the n− region 2.In the known diode 10 the current gain may be very high because therecombination in said regions is very low due to the long recombinationlifetime of charge carriers in (bulk) silicon. In addition, the lateraldiffusion-capability of holes is limited because the base region 3 isdepleted during operation. Thus, BVCEO is low. In a device 10 inaccordance with the invention, on the one hand, the furthersemiconductor region 7, which in the example discussed is of the pconductivity type, offers an escape route for the holes generated byimpact ionization. As this region 7 is, as it were, distributed over thefirst semiconductor region 1 this escape route is present everywhereand, at least in the lateral direction, the holes do not have to bridgea distance to reach this escape route and can readily flow from the base1 to the emitter 4. As the holes can be readily drained, the occurrenceof collector-emitter breakdown is precluded and hence also theoccurrence of instability (oscillation) caused by negative resistancebehavior. On the other hand, the first, n-type, semiconductor region 1divided into parts 1A still provides excellent contact for the mainconstituent of the electric current through the device 10, i.e. theelectron current. As a result, the I-V characteristic is very steep,which is highly desirable.

Doping concentrations found to be suitable for the first, second, thirdand fourth semiconductor region 1, 2, 3, 4 are at least, respectively,10¹⁷ to 10²⁰ at/cm³, 10¹⁴ to 10¹⁷ at/cm³, 10¹⁶ to 10¹⁸ at/cm³ and 10¹⁷to 10²⁰ at/cm³. In this example, said doping concentrations are,respectively, 5×10¹⁸, 10¹⁵, 10¹⁷ and 10¹⁸ at/cm³. This variation of thedoping concentrations in the device 10 in accordance with the inventionis diagrammatically shown in FIG. 3. The thicknesses of said regions 1,2, 3, 4 are in this case 10 nm, 1 μm, 200 nm and 300 μm, respectively.More generally it can be said that the fourth region 4 comprises atleast ten times the doping level of the third region 3, and the secondregion 2 comprises less than one tenth of the doping level of the thirdregion 3. If, unlike this example, the second region 2 is a p− region,then it applies to the second and third region 2, 3 that the sum of theproducts of thickness and doping concentration is approximately 2×10¹²at/cm².

In this example, the semiconductor body 12 comprises a mesa-shaped part12A which is approximately square and measures 200×200 μm², and whichhas a height of 2 μm and comprises at least the fourth, third and secondsemiconductor region 4, 3, 2 and, in this case, also a part of the firstregion 1, and the walls of which are covered with an isolating layer111, in this case of silicon dioxide having a thickness of 300 nm, whichis provided with apertures accommodating the connection conductors 5, 6.At the location of the junction between the p+ region 3 and the n−region 2 there is a p+ region 9 at the edge of the mesa 12A, which p+region serves as a so-termed guard ring and prevents a prematurepunchthrough near the edge of the mesa 12A. The two connectionconductors 5, 6 contain 10 nm AlSo, 100 nm TiW(N) and 0.5 μm Al. Thelateral dimensions of the semiconductor device 12 are approximately 10μm larger than the mesa-shaped part 12A thereof. In addition, in thisexample, the further semiconductor region 7 comprises, on the outside ofthe mesa 12A, a wider portion 7A which, in this case, is 20 μm wide,while the other parts of the further semiconductor region 7 which aresituated between the sub-regions 1A have a width of 2 μm, just like thesub-regions 1A of the first semiconductor region 1.

FIGS. 4 through 10 are diagrammatic cross-sectional views at rightangles to the thickness direction, of the device of FIG. 1 in successivestages of the manufacture by means of a method in accordance with theinvention. An n-type Si substrate 11 (see FIG. 4) is used as thestarting material. An epitaxial layer 14 of lightly doped silicon isdeposited on the substrate 11, in this case by means of non-selectivegas-phase epitaxy at a temperature of 700° C. Next (see FIG. 5) a p-typeion implantation is carried out, causing the entire epitaxial layer 14to become p+ type and the further semiconductor region 7 to be formed.Subsequently, the semiconductor body 12 is provided with a mask, notshown in the drawing, and the sub-regions 1A of the first semiconductorregion 1 as well as the other semiconductor region 8 are formed by meansof an n+ ion implantation that reaches at least as far as the junctionbetween the further semiconductor region 7 and the substrate 11.

Next (see FIG. 6) a stack of layers 2, 3, 4 is epitaxially provided fromwhich the second, third and fourth semiconductor region 2, 3, 4 will beformed. Next (see FIG. 7) a mask 70 is provided that serves as an etchmask during an etching process wherein a mesa 71 is formed thatcomprises the fourth semiconductor region 4 and a (large) part of thethird semiconductor region 3. Subsequently (see FIG. 8) a p+ ionimplantation is carried out, thereby forming the guard ring 9. Next,so-termed spacers 80 are formed against the walls of the mesa 71 in acustomary manner.

The etching operation of the semiconductor body 12 is now continued (seeFIG. 9), thereby forming the mesa-shaped part 12A thereof, and saidoperation reaching into the further semiconductor region 7. Next, a maskis used, which is not shown in the Figure, to form the other n+semiconductor region 8 by means of ion implantation. Subsequently (seeFIG. 10), after removal of the spacers 80, the semiconductor body 12,12A is covered with an isolating layer 111 which is provided withapertures, as shown in the Figure, and at the location of said aperturesthe connection conductors 5, 6 are formed from a deposited and patternedconductor layer. At this stage, the device 10 in accordance with theinvention is ready for final assembly. If a large number ofsemiconductor devices 10 in accordance with the invention aresimultaneously formed in a single semiconductor body 12, individualdevices 10 can be obtained by applying a separation process such assawing.

FIG. 11 is a diagrammatic cross-sectional view at right angles to thethickness direction, of a second example of a semiconductor device inaccordance with the invention. The most essential difference between thedevice 10 of this example and that of the first example is that thefirst, second, third and fourth semiconductor region 1, 2, 3, 4 aresituated in a reversed order with respect to the substrate 11. Inaddition, the fourth semiconductor region 4 is formed, in this case, bythe substrate 11 itself, which is not essential however. The sub-regions1A of the first semiconductor region 1 and the further semiconductorregion 7 border directly on the first connection conductor 5 which issituated, in this case, on top of the semiconductor body 12. The device10 of this example has various advantages, such as the possibility ofaccurately forming and defining the further semiconductor region 7,which in this case is situated close to the service of the semiconductorbody 12, by means of ion implantation. Also the manufacture of thedevice 10 is comparatively simple because all semiconductor regions 1,2, 3, 4 can be provided in a single epitaxial growth process. The device10 of this example can of course be provided with a guard ring like inthe first example. The manufacture can be readily adapted thereto.

FIG. 12 shows the current density (J) as a function of the voltage (B)of the device of FIG. 11 for different values of the width of the widestpart 7A of the further semiconductor region 7. Curves 120, 121, 122 and123 correspond to a width of said part 7A of 1, 5, 10 and 20 μm,respectively. These results clearly show that a particularly useful I-Vcharacteristic is found at a width in excess of approximately 5 μm.

The invention is not limited to the exemplary embodiment describedabove, and, within the scope of the invention, many modifications andvariations are possible to those skilled in the art. For example otherthicknesses, other (semiconductor) materials or other compositions thanthose mentioned in the example can be applied. Also, all conductivitytypes used can be simultaneously replaced by the opposite. Variousprocess steps which are not relevant for the invention can also becarried out in a different manner, for example an oxide layer obtainedby plasma deposition may also be formed by deposition from the gasphase.

It is finally noted that the application of the device and the method inaccordance with the invention is not limited to discrete devices. Other(semiconductor) components can be integrated into the semiconductorbody.

1. A semiconductor device with a semiconductor body, the devicecomprising: a substrate of a first conductivity type; a firstsemiconductor region that includes a plurality of sub-regions of thefirst conductivity type that have a first doping concentration and afurther semiconductor region of a second conductivity type opposite tothe first conductivity type, the further semiconductor regionsurrounding each of the sub-regions and separating the sub-regions fromeach other, the first semiconductor region located on the substrate,wherein the sub regions extend from the second semiconductor region intothe substrate; a second semiconductor region of the first conductivitytype and having a second doping concentration which is lower than thefirst doping concentration, the second semiconductor region located onthe first semiconductor region; a third semiconductor region of thesecond conductivity type and having a third doping concentration rangingbetween the first and the second doping concentration, the thirdsemiconductor region located on the second semiconductor region; afourth semiconductor region of the first conductivity type and having afourth doping concentration which is higher than the third dopingconcentration, the fourth semiconductor region located on the thirdsemiconductor region, and wherein the fourth doping concentration ishigher than the first doping concentration; a first electric connectionconductor that is located on a side of the semiconductor body and thatis electrically connected to the further semiconductor region; and asecond electric connection conductor that is located on and electricallyconnected to the fourth semiconductor region, wherein an electricvoltage is applied across the first and second connection conductorsduring operation of the device, and wherein the thickness and the dopingconcentration of the second and the third semiconductor region are suchthat these regions are completely depleted during operation of thedevice.
 2. A method of manufacturing a semiconductor device having asemiconductor body with a substrate of a first conductivity type, themethod comprising: forming a first semiconductor region on thesubstrate, the first semiconductor region including a plurality ofsub-regions of the first conductivity type that have a first dopingconcentration and a further semiconductor region of a secondconductivity type, which is opposite to the first conductivity type,that separates each of the sub-regions from each other; forming a secondsemiconductor region of the first conductivity type on the firstsemiconductor region, the second semiconductor region having a seconddoping concentration that is lower than the first doping concentration;forming a third semiconductor region of the second conductivity type onthe second semiconductor region, the third semiconductor region having athird doping concentration ranging between the first and the seconddoping concentration; forming a fourth semiconductor region of the firstconductivity type on the third semiconductor region, the fourthsemiconductor region having a fourth doping concentration that is higherthan the third doping concentration, forming a first electric connectionconductor that is electrically connected to the further semiconductorregion; forming a second electric connection conductor on the fourthsemiconductor region, the second electric connection conductor beingelectrically connected to the fourth semiconductor region; and forminganother semiconductor region of the first conductivity type on thesubstrate, the another semiconductor region having a higher dopingconcentration than the substrate, wherein the another semiconductorregion is connected to the substrate, to the first electric connectionconductor, and to the further semiconductor region, wherein an electricvoltage is applied across the first and second electric connectionconductors during operation of the device, wherein the thickness and thedoping concentration of the second semiconductor region are chosen suchthat, during operation, the second semiconductor region is completelydepleted, wherein the first semiconductor region is formed on thesubstrate by applying a lightly doped epitaxial semiconductor layer,which is provided with the second conductivity type by means of an ionimplantation that reaches at least as far as the substrate, as a resultof which the further semiconductor region is formed, and wherein thesub-regions of the first semiconductor region and the anothersemiconductor region are formed by further ion implantation that reachesat least up to the substrate, after which the second, third and fourthsemiconductor regions are formed by epitaxy.